Method for forming a floating gate using chemical mechanical planarization

ABSTRACT

An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices and,in particular, to a method for forming floating gate regions.

BACKGROUND OF THE INVENTION

A nonvolatile memory is a type of memory that retains stored data whenpower is removed. There are various types of nonvolatile memoriesincluding e.g., read only memories (ROMs), erasable programmable readonly memories (EPROMs), and electrically erasable programmable read onlymemories (EEPROMs). One type of EEPROM device is a flash EEPROM device(also referred to as “flash memory”).

Each nonvolatile memory device has its own unique characteristics. Forexample, the memory cells of an EPROM device are erased using anultraviolet light, while the memory cells of an EEPROM device are erasedusing an electrical signal. In a conventional flash memory device blocksof memory cells are simultaneously erased (what has been described inthe art as a “flash-erasure”). The memory cells in a ROM device, on theother hand, cannot be erased at all. EPROMs, and EEPROMs, includingflash memory, are commonly used in computer systems that requirereprogrammable nonvolatile memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include, e.g., portable computers, personaldigital assistants (PDAs), digital cameras, portable music players, andcellular telephones. Program code, system data such as a basicinput/output system (BIOS), and other firmware can typically be storedin flash memory devices.

FIGS. 1A-1G depict one conventional process of forming floating gateregions for one-transistor storage cells of non-volatile memory devices.

As shown in FIG. 1A, a pad oxide layer 12 is formed on a siliconsubstrate 11. A nitride layer 13 is then formed on top of the pad oxide12. Trenches 14 are formed in the resulting structure, as shown in FIG.1B. An oxide layer 15 is deposited within the trenches 14 and on top ofthe nitride layer 13. The resulting structure is shown in FIG. 1C.

Standard STI chemical mechanical planarization (CMP) is used to isolatethe active regions of the device. The conventional STI CMP process usesthe nitride layer 13 as a stop layer. The structure resulting from theSTI CMP process is illustrated in FIG. 1D. As shown in FIG. 1E, afterthe STI CMP process, the nitride layer 13 and the pad oxide layer 12 arestripped, thus exposing the active areas 18.

After the nitride layer 13 and pad oxide layer 12 are stripped, a gateoxide layer 16 and a polysilicon layer 17 are deposited (FIG. 1F). Thepolysilicon layer 17 will form the floating gate of completedone-transistor flash memory cells. As is shown in FIG. 1F, polysilicon17 is deposited over the active areas and the oxide 15. A self alignedfloating gate (SAFG) CMP process is then implemented to remove excesspolysilicon 17 and to isolate the polysilicon 17 in the active areas 18.

The SAFG CMP process is very demanding. The amount of polysilicon 17left behind over the active areas 18 depends on the field leveling inthe array and periphery, oxide dishing in the periphery, array center toedge doming, and the amount of nitride remaining. Dishing refers to thethinning of a structure, caused by uneven polishing based on theselectivity of the slurry being used, resulting in a dish-like profilewhen measured in reference to the surrounding material. For example,when polishing oxide and stopping on nitride, the slurry used istypically selective to nitride, so when the polish hits nitride, itpolishes oxide faster than nitride, resulting in a dish-like profile inthe oxide at the level of the nitride. Doming is the opposite ofdishing, resulting in a dome-like profile. Doming is usually caused byfill pattern issues. The SAFG CMP needs to be highly selective to theoxide 15 with good polysilicon 17 polishing rate; however, the CMPshould not cause dishing in the polysilicon 17.

It is desirable to integrate the above described STI CMP and SAFG CMPsteps into a single process flow to overcome the above-notedshortcomings. Accordingly, a simplified process for forming a floatinggate region of the transistor storage cells of a non-volatile memorydevice is needed and desired.

BRIEF DESCRIPTION OF THE DRAWINGS

The above described features of the invention will be more clearlyunderstood from the following detailed description, which is providedwith reference to the accompanying drawings.

FIGS. 1A-1G illustrate a method of manufacturing a floating gate regionof a non-volatile memory device according to the prior art;

FIGS. 2A-2D illustrate a method of manufacturing a floating gate regionof a non-volatile memory device according to a first exemplaryembodiment of the invention;

FIGS. 3A-3D illustrate a method of manufacturing a floating gate regionof a non-volatile memory device according to a second exemplaryembodiment of the invention;

FIG. 4 illustrates an intermediate processing step of a third exemplaryembodiment of the invention, which fits between the steps of FIGS. 2Cand 2D; and

FIG. 5 illustrates a flash memory device including a floating gateregion formed in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a method of manufacturing non-volatilememory devices having memory cell transistors with floating gates.

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and show by way ofillustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and that changesmay be made without departing from the spirit and scope of the presentinvention. The progression of processing steps described is exemplary ofembodiments of the invention; however, the sequence of steps is notlimited to that set forth herein and may be changed as is known in theart, with the exception of steps necessarily occurring in a certainorder.

The term “substrate” is used in the following description to refer toany supporting layer suitable for fabricating an integrated circuit,typically semiconductor based, but not necessarily so. A substrate maybe silicon-based, may include epitaxial layers of silicon supported by abase semiconductor or non-semiconductor foundation, can besapphire-based, silicon-on-insulator (SOI), metal, polymer, or any othersuitable materials. When reference is made to a substrate in thefollowing description, previous process steps may have been utilized toform regions, junctions or other structures in or over a basesemiconductor or other foundation.

Additionally, while exemplary embodiments of the invention are describedin connection with flash memory, the invention is not so limited. Theinvention is applicable to other integrated circuit devices and systems,which might employ floating gate structures.

The invention relates to an improved method for forming a floating gatesemiconductor device. The method uses an improved chemical mechanicalplanarization (CMP) process to form a self-aligned floating gate region,which requires less steps than the number of steps used in the priorart.

An first exemplary embodiment of the invention is described below inconnection with FIGS. 2A-2D. A similar second exemplary embodiment isalso described in connection with FIGS. 3A-3D. A third exemplaryembodiment is described in connection with FIG. 4.

As shown in FIG. 2A, a gate oxide layer 116 is formed over a siliconsubstrate 111. A thick polysilicon layer 117 is formed over the gateoxide layer 116. Next, a thin nitride layer 113 is formed over thepolysilicon layer 117. The thickness of the nitride layer 113 may be inthe range of about 50 Å to about 150 Å thick. The thin nitride layer 113enables the thicker polysilicon layer 117 to be used. The thickness ofthe final polysilicon layer 117 (FIG. 2D) may be in the range of about400 Å to about 1000 Å thick.

As shown in FIG. 2B, trenches 114 are formed in the resulting structure,by any process known in the art for forming shallow trench isolation(STI) regions. An oxide layer 115 is then deposited within the trenches114 and on top of the nitride layer 113, as is shown in FIG. 2C. Theoxide layer 115 may be formed of, for example, a high density plasma(HDP) oxide, O3-TEOS oxide, spin on dielectric (SOD), or any othersuitable oxide known in the art.

In a second exemplary embodiment of the invention, the nitride layer 113may be eliminated, as shown in FIGS. 3A-D. In the case of the secondembodiment, the oxide layer 115 is deposited directly on top of thepolysilicon layer 117, as shown in FIG. 3C. Like reference numerals inFIGS. 3A-D refer to the same elements as in FIGS. 2A-D and are notdiscussed in detail herein.

In both the first and second embodiments, chemical mechanicalplanarization (CMP) is performed during which the oxide layer 115 ispartially removed and planarized. As the oxide 115 is being removed inthe first embodiment, the CMP process will reach the nitride layer 113.The slurry used in the CMP process of the invention has the capabilityto remove nitride as well as the oxide. Thus, the thin nitride layer 113of the first embodiment can be easily removed. As explained below, theselectivity of the slurry allows the process to stop on polysiliconlayer 117. Thus, polysilicon layer 117 acts as the stop layer for theCMP process of the invention. In the second embodiment, the CMP processremoves the oxide layer 115 and stops on the polysilicon layer 117, aswell. The result is a desired thickness of polysilicon 117 in betweenthe oxide areas 115. The resulting floating gate region 110 is shown inFIGS. 2D and 3D. The floating gates 120 are the remaining portions ofpolysilicon layer 117, insulated from each other by the oxide areas 115.As can be seen, this process requires fewer steps than the conventionalprocess for forming floating gate regions.

An additional benefit of the process is that the slurry used providesenough over-polish margin to clear any oxide 115 and/or nitride 113residuals. Moreover, polysilicon residue over “dished” oxide areas isalso eliminated since there is no polysilicon deposited over the oxideareas during the process.

The STI CMP process of the present invention provides “stop onpolysilicon” capability. The slurry used in the present invention is aceria slurry. A ceria slurry is a slurry comprised of cerium oxide(CeO₂) particles. The ceria slurry of the invention includes CeO₂particles which may have a mean particle size in the range of about 0.1μm to about 1.5 μm. The ceria slurry has a solids percentage betweenabout 1% and about 7%. Before use, the slurry is mixed with any cationicand/or any anionic additive. The solids percentage at the point of usemay be between about 1% and about 4%. An example of an appropriateadditive includes cationic cetyl trimethyl ammonium bromide (CTAB)additive. Post mixing of the slurry and additive should yield a pH rangebetween about 5 and about 8. The ceria slurry with the additive, whenmixed in the above specified ratios, provides the necessary oxide andnitride rate with selectivity and planarization capability along withgood selectivity to polysilicon. Controlling the solids percentage, pH,and mix ratio can alter the selectivity between oxide, nitride, andpolysilicon. Higher pH tends to increase polysilicon rate and decreasenitride rate, while higher solids percentage has a low impact onpolysilicon rate but increases nitride rate significantly.

In a third exemplary embodiment, the addition of the additives to theslurry may occur after the stop on nitride using traditional STI CMP isachieved. In this case, a standard STI slurry will be used to remove theoxide layer 115 and stop on nitride 113, as shown in FIG. 4. Beyond thatpoint, a slurry of the invention formulated to have a 1:1:1 or 0.5:1:1poly:nitride:oxide selectivity will be used to remove the nitride layer113 and stop on polysilicon 117. This process requires an intermediateprocessing step between FIGS. 2C and 2D, illustrated in FIG. 4.

As shown in FIG. 5, the floating gate region formed in accordance withthe invention may be included as part of a flash memory structure 130.The oxide 115 provides insulation between the floating gates 120. Oxidelayer 122 is formed above the floating gates 120 and the oxide 115.Control gates 124 are formed above the floating gates 120 and the oxidelayer 122. Oxide 126 provides insulation between the control gates 124.The control gates 124 and oxide 126 are formed as is known in the art.

The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the invention. Although exemplary embodiments of thepresent invention have been described and illustrated herein, manymodifications, even substitutions of materials, can be made withoutdeparting from the spirit or scope of the invention. Accordingly, theabove description and accompanying drawings are only illustrative ofexemplary embodiments that can achieve the features and advantages ofthe present invention. It is not intended that the invention be limitedto the embodiments shown and described in detail herein. The inventionis limited only by the scope of the appended claims.

1. A method of forming a floating gate region comprising the acts of:providing a first insulating layer over a substrate; providing aconductive layer over the first insulating layer; forming a trenchextending through the conductive layer and the first insulating layerand into the substrate; providing a second insulating layer over theconductive layer and within the trench; and planarizing the secondinsulating layer and any intermediate layers to remove all of the secondinsulating layer that is above the conductive layer, wherein the processused for planarization is a chemical mechanical planarization processthat has characteristics which cause the planarization to stop when itreaches the conductive layer, wherein the floating gate region comprisesa portion of the conductive layer which remains after the trench isformed and upon which the planarization stops, and wherein the secondinsulating layer within the trench forms an isolation regioncorresponding to the floating gate region.
 2. The method of claim 1,further comprising providing a third insulating layer over theconductive layer, and wherein the trench extends through the thirdinsulating layer.
 3. The method of claim 1, wherein the first insulatinglayer comprises an oxide.
 4. The method of claim 1, wherein theconductive layer comprises polysilicon.
 5. The method of claim 1,wherein the second insulating layer comprises an oxide.
 6. The method ofclaim 1, wherein the chemical mechanical planarization process utilizesa slurry chosen to selectively remove only the second insulating layerand any intermediate layers but not the conductive layer.
 7. The methodof claim 1, wherein the trench surrounds the floating gate region. 8.The method of claim 2, wherein the third insulating layer comprisesnitride.
 9. The method of claim 2, wherein the planarizing stepcomprises: a first chemical mechanical planarization process utilizing afirst slurry which removes the second insulating layer; and a secondchemical mechanical planarization process utilizing a second slurrycomprising CeO₂ particles and an additive which removes the thirdinsulating layer, wherein the second slurry is chosen to selectivelyremove the third insulating layer and not the conductive layer.
 10. Themethod of claim 4, wherein the polysilicon layer has a thickness ofapproximately 400 Å to 1000 Å.
 11. The method of claim 8, wherein thenitride layer has a thickness of approximately 50 Å to 150 Å.
 12. Themethod of claim 6, wherein the chemical mechanical planarization processalso removes a third insulating layer provided between the conductivelayer and the second insulating layer.
 13. The method of claim 6,wherein the slurry comprises CeO₂ particles.
 14. The method of claim 6,wherein the slurry has a solids percent within a range of about 1% andabout 7%.
 15. The method of claim 6, wherein the slurry is mixed with anadditive.
 16. The method of claim 13, wherein the CeO₂ particles have amean particle size of between approximately 0.1 μm and 1.5 μm.
 17. Themethod of claim 14, wherein the slurry has a solids percent within arange of about 1% and about 4%.
 18. The method of claim 15, wherein theadditive is cationic.
 19. The method of claim 15, wherein the additiveis anionic.
 20. The method of claim 15, wherein the additive is cetyltrimethyl ammonium bromide.
 21. The method of claim 15, wherein theslurry has a pH within a range of about 5 and about
 8. 22. A method offorming a plurality of floating gate regions comprising the acts of:providing a first oxide layer over a substrate; providing a polysiliconlayer over the first oxide layer; providing an insulating layer over thepolysilicon layer; forming a plurality of trenches extending through theinsulating layer, the polysilicon layer, the first oxide layer and intothe substrate; providing a second oxide layer over the insulating layerand within the plurality of trenches; and planarizing the second oxidelayer and the insulating layer to remove all of the second oxide layerthat is above the plurality of trenches and to remove the insulatinglayer, the process used for planarization having characteristics whichcause the planarization to stop when it reaches the polysilicon layer,wherein the floating gate regions comprises portions of the polysiliconlayer which remain after the plurality of trenches is formed and uponwhich the planarization stops, and wherein the plurality of floatinggate regions are isolated from each other by the second oxide layerprovided within the plurality of trenches.
 23. The method of claim 22,wherein the insulating layer is a nitride layer.
 24. The method of claim22, wherein the polysilicon layer has a thickness of approximately 400 Åto 1000 Å.
 25. The method of claim 22, wherein the planarizing steputilizes a chemical mechanical planarization process which utilizes aslurry chosen to selectively remove only the second oxide and insulatinglayers.
 26. The method of claim 23, wherein the nitride layer has athickness of approximately 50 Å to 150 Å.
 27. The method of claim 25,wherein the slurry comprises CeO₂ particles.
 28. The method of claim 25,wherein the slurry has a solids percent within a range of about 1% andabout 7%.
 29. The method of claim 25, wherein the slurry is mixed withan additive.
 30. The method of claim 27, wherein the CeO₂ particles havea mean particle size of between approximately 0.1 μm and 1.5 μm.
 31. Themethod of claim 29, wherein the additive is at least one of a cationicadditive and an anionic additive.
 32. The method of claim 29, whereinthe additive is cetyl trimethyl ammonium bromide.
 33. The method ofclaim 29, wherein the slurry has a pH within a range of about 5 andabout
 8. 34. A method of forming a floating gate region comprising theacts of: providing a first insulating layer over a substrate; providinga conductive layer over the first insulating layer; providing a secondinsulating layer over the conductive layer, wherein the secondinsulating layer comprises nitride and is formed directly on andcontiguous with a top surface of the conductive layer; forming a trenchextending through the second insulating layer, the conductive layer andthe first insulating layer and into the substrate, the trench beingformed to create at least one isolated portion of the conductive layer;providing a third insulating layer over the conductive layer and withinthe trench; and removing the third insulating layer that is over thetrench and removing the second insulating layer, wherein removing boththe second and third insulating layers is accomplished by planarizationwhich stops at the conductive layer, wherein the floating gate regioncomprises the isolated portion of the conductive layer which remainsafter the trench is formed and upon which the planarization stops.
 35. Amethod of forming a floating gate region comprising the acts of:providing a first insulating layer over a substrate; providing aconductive layer over the first insulating layer; forming a trenchextending through the conductive layer and the first insulating layerand into the substrate, the trench being formed to create an isolatedportion of the conductive layer; providing a second insulating layerdirectly on and contiguous with a top surface of the conductive layerand within the trench; and planarizing all of the second insulatinglayer that is above the conductive layer, wherein the planarizationstops at the conductive layer, wherein the floating gate regioncomprises the isolated portion of the conductive layer which remainsafter the trench is formed and upon which the planarization stops.
 36. Amethod of forming a floating gate region comprising the acts ofproviding a first insulating layer over a substrate; providing aconductive layer over the first insulating layer; forming a trenchextending through the conductive layer and the first insulating layerand into the substrate; providing a second insulating layer over theconductive layer and within the trench; planarizing the secondinsulating layer and any intermediate layers to remove all of the secondinsulating layer that is above the conductive layer, wherein theplanarization stops at the conductive layer, subsequent to the act ofplanarizing the second insulating layer and any intermediate layers,providing a third insulating layer over exposed portions of the secondinsulating layer and conductive layer; and providing a control gate overthe third insulating layer, wherein planarizing the second insulatinglayer and any intermediate layers isolates the floating gate regionwhich comprises a remaining portion of the conductive layer.